F. Eibensteiner, J. Kogler, Josef Scharinger,
"A High-Performance Hardware Architecture for a Frameless Stereo Vision Algorithm Implemented on a FPGA Platform."
: Proceedings of the 10th IEEE Embedded Vision Workshop (held in conjunction with IEEE CVPR), Columbus, USA., 2014
Original Titel:
A High-Performance Hardware Architecture for a Frameless Stereo Vision Algorithm Implemented on a FPGA Platform.
Sprache des Titels:
Englisch
Original Buchtitel:
Proceedings of the 10th IEEE Embedded Vision Workshop (held in conjunction with IEEE CVPR), Columbus, USA.
Forschungs-