Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study
Sprache des Vortragstitels:
Forum on specification & Design Languages (FDL)
Sprache des Tagungstitel:
Extensive processor verification at the RegisterTransfer Level (RTL) is crucial to avoid bugs. Therefore, simulation-based approaches are prevalent but they require efficient test generation methods to achieve a thorough verification. In this paper we propose an efficient cross-level testing approach for processor verification targeting the RISC-V Instruction Set Architecture (ISA). We generate an endless instruction stream without restrictions on the generated instructions by evolving the instruction stream on-the-fly during simulation. An Instruction Set Simulator (ISS) is leveraged as reference model for the RTL core under test in a tightly coupled crosslevel co-simulation setting. This enables a very efficient and comprehensive testing process. As a case-study we present results on the verification of the 32 bit pipelined RISC-V core of MINRES The Good Folk (TGF) Series Our approach has been very effective in finding several serious bugs.