Early Verification of ISA Extension Specifications using Deep Reinforcement Learning
Sprache des Vortragstitels:
Englisch
Original Tagungtitel:
ACM Great Lakes Symposium on VLSI (GLSVLSI)
Sprache des Tagungstitel:
Englisch
Original Kurzfassung:
For IoT devices the demand in faster execution and at the same time
lower energy consumption is a pressing problem. A very promising
solution are Application-Specific Instruction-set Processors (ASIPs).
They make use of custom instructions, which are added to the
processor, forming the Instruction-Set Extension (ISE) of a given
Instruction Set Architecture (ISA). While the selection process for
the ISE is already challenging, an incorrect ISE specification leads
to severe problems: errors and security vulnerabilities go undetected in the first formalization and in the worst case show up
ultimately in the final implementation. In this paper, we propose
an early verification approach for ISE specifications. Our novel
approach is based on two ingredients: (i) Virtual Prototypes (VPs)
to enable a rapid creation of an executable specification for the
ISE; and (ii) Deep Reinforcement Learning (DRL) to search for ISE
programs which violate the ISE specification intent. As case study
we consider extensions of the RISC-V base ISA. We demonstrate
the effectiveness of our approach for finding functional bugs in the
executable specification of the ISE as well as specification gaps in
the ISE leading to information leakage.
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