A 1.2-V, 1.8-GHz Low-Power PLL Using a Class-F VCO for Driving 900-MHz SRD Band SC-Circuits
Sprache des Vortragstitels:
ACM/IEEE International Symposium on Low Power Electronics and Design ISLPED 2020
Sprache des Tagungstitel:
This work presents a 1.6 GHz to 2 GHz integer PLL with 2 MHz stepping, which is optimized for driving low-power 180 nm switched-capacitor (SC) circuits at a 1.2 V supply. To reduce the overall power consumption, a class-F VCO is implemented. Due to enriched odd harmonics of the oscillator, a rectangular oscillator signal is generated, which allows omitting output buffering stages. The rectangular signal results in a lowered power consumption and enables to directly drive SC-filters and an RF-divider using the oscillator signal. In addition, the proposed RF-divider includes a differential 4-phase signal generation at 868 MHz and 915 MHz SRD band frequencies that can be used for complex modulation schemes. With a fully integrated loop-filter, a maximum of integration is achieved. A test-chip was manufactured in a 1P6M 180 nm CMOS technology
with triple-well option and confirms a PLL with a total active power consumption of 4.1mW. It achieves a phase noise of ?111 dBc/Hz at 1 MHz offset and a ?42 dBc spurious response from a 1 MHz reference.