Bogdan Matasaru, Tudor Jebelean,
"FPGA Implementation of an Extended Binary GCD Algorithm for Systolic Reduction of Rational Numbers"
: Proceedings of Field Programmable Logic and Applications, in Lecture Notes in Computer Science, Serie Lecture Notes in Computer Science, 12-2000, B.Matasaru, T. Jebelean, Proceedings of FPL 2000: Field Programmable Logic and Applications, Aug. 28-30, Villach, Austria, Springer (LNCS 1896), 2000, pages 810-813
Original Titel:
FPGA Implementation of an Extended Binary GCD Algorithm for Systolic Reduction of Rational Numbers
Sprache des Titels:
Englisch
Original Buchtitel:
Proceedings of Field Programmable Logic and Applications
Englischer Titel:
FPGA Implementation of an Extended Binary GCD Algorithm for Systolic Reduction of Rational Numbers
Journal:
Lecture Notes in Computer Science
Serie:
Lecture Notes in Computer Science
Erscheinungsmonat:
12
Erscheinungsjahr:
2000
Notiz zum Zitat:
B.Matasaru, T. Jebelean, Proceedings of FPL 2000: Field Programmable Logic and Applications, Aug. 28-30, Villach, Austria, Springer (LNCS 1896), 2000, pages 810-813
Forschungs-