"Hardware architecture for learning Random Forests"
Hardware architecture for learning Random Forests
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The importance of machine learning techniques has risen enormously over the last decade. Next to the well-known neural network approach, random forests is a further technique utilized in diverse fields such as autonomous driving, communications or consumer electronics. In particular, random forests will be considered, which exploit the supervised learning technique and are furthermore applied to regression problems. In literature, a learning approach of random forests implemented in digital hardware has been documented. These works, however, have the disadvantage that a computationally expensive online sorting algorithm is required. In this master thesis a novel, efficient learning approach will be provided in very high speed integrated circuit hardware description language (VHDL), without the necessity for an online sorting algorithm. To validate the implemented hardware architecture, two regression problems will be investigated. Additionally, a clock cycle estimation will be derived and synthesis results will be considered. As a result, the linear dependency of the clock cycle approximation will be presented as well as how many random forests can be learned in one second. Finally, a conclusion is drawn and an outlook for a possible extension of this thesis will be provided.