Generic Error Localization for the Electronic System Level
Sprache des Titels:
Englisch
Original Buchtitel:
DDECS 2019
Original Kurzfassung:
Several methods and tools have been proposed
which supports designers in verifying embedded systems in
early phases of the design process, e.g. at the Electronic System
Level (ESL). However, they only show whether an error indeed
exists in the system, but it frequently remains open to efficiently
locate the source of this error. In this work, we propose a generic
error localization methodology. More precisely, by applying code
augmentations and conducting further runs of the verification
method, it is analyzed what statements may have caused the
error. The respectively determined statements then pin-point the
verification engineer to possible error locations. By conducing
all this on the code level only, the proposed methodology can be
applied to any verification method available today. The suitability
of the proposed methodology is demonstrated by means of a
verification flow based on symbolic execution.
Forschungs-