Alwin Walter Zulehner, Robert Wille,
"Skipping Embedding in the Design of Reversible Circuits"
: International Symposium on Multiple-Valued Logic (ISMVL), Seite(n) 173-178, 2017
Skipping Embedding in the Design of Reversible Circuits
Sprache des Titels:
International Symposium on Multiple-Valued Logic (ISMVL)
Synthesis of reversible circuits finds application in
many promising domains but has to deal with the fact that the
underlying circuits require a unique mapping from the inputs
to the outputs. Existing solutions addressed this problem by
additionally performing a so-called embedding process prior to
synthesis or by naively mapping building blocks of conventional
logic to their corresponding reversible counterparts. This leads
to solutions that either suffer from limited scalability or yield circuits
with a huge number of additionally required circuit lines. In
this work, we conduct investigations to overcome these problems.
To this end, we simply ignore the fact that an arbitrary Boolean
function to be synthesized might be non-reversible and deal with
the resulting problem of ensuring a unique input/output mapping
during the actual synthesis process. Experimental evaluations
indicate that, following this approach, could provide the basis
for an alternative synthesis scheme that allows for synthesizing
arbitrary Boolean functions in reasonable time and without the
need of a prior embedding process.