Ameliorating the bias stress stability of n-type OFETs
Sprache des Titels:
he bias stress effect on C60 based n-type OFETs was studied comprehensively. The role of dielectric layers and the active layers on bias stress effect was quantified by choosing three different dielectric layers with three different morphologies of active layers. It was found, that the bias stress induced charges can be trapped in active layer as well as in dielectric layers. The charge trapping in active layers happened ten times faster as compared to the trapping of charges in dielectric layers. It was proved, that the use of appropriate dielectric layers increases the bias stress stability by decreasing bias stress effects up to 55%. It was experimentally proven that the fabrication of electrically stress stable devices is possible by using C60 layers grown at higher substrate temperature or with large grain sizes. The OFETs fabricated with larger grain sizes also fulfil the criterion of Guard bands for modelling of electronic circuits, which is a first step of organic electronics towards the industrialization. On the basis of experimental evidences, the criterion of choosing appropriate dielectric layers for OFETs was also proposed.